1. Field of the Invention
The present invention relates to a latch circuit, and more particularly, to a pulse latch circuit.
2. Description of Related Art
In order to detect deterioration of a circuit, which is tested for detecting the deterioration, of an LSI (Large Scale Integrated Circuit), the test is performed by inserting in parallel two flip-flop (FF) circuits to an output bus of the circuit to be tested. A delay amount of each of the two flip-flop circuits is different with each other. The two FF circuits may latch an output data of the circuit to be tested when the deterioration of the circuit to be tested is small. However, an FF circuit including a larger delay may not latch the output data of the circuit to be tested when the deterioration of the circuit to be tested becomes large.
In recent years, regarding the LSI, a pulse latch circuit has been substituted for the FF circuit for increasing an operation speed of the LSI. The pulse latch circuit operates according to a pulse-shaped clock signal. Regarding the pulse latch circuit, an improvement technique is proposed from various viewpoints.
For example, in patent document 1 (Japanese Patent Laid-Open No. 2006-339948), a technique which reduces a power consumption of the pulse latch circuit is disclosed. This technique will be described with reference to FIG. 12.
FIG. 12 shows a pulse latch circuit 1 to which the technique of the patent document 1 is applied. The pulse latch circuit 1 includes a latch circuit 10, a latch circuit 11, a selector 12, and a latch control circuit 13. The selector 12 transmits selectively input data D and scan input data SI for a scan shift to the latch circuit 10 according to a scan enable signal SE. The latch circuit 10 latches an output of the selector 12 according to the pulse shaped clock signal (hereinafter, a pulse clock signal) PCLK. The latch circuit 11 passes through a signal during when the pulse clock signal PCLK is Low. An operation of the latch circuit 11 is controlled by the latch control circuit 13. The pulse clock signal PCLK is provided to the latch circuit 11 for operating the latch circuit 11 during when the scan enable signal SE is high. The pulse clock signal PCLK is not provided to the latch circuit 11 during when the scan enable signal SE is low. Therefore, the latch circuit 11 stops the operation.
The latch circuit 11 passes through the scan input data SI which is latched by the latch circuit 10 when the scan enable signal SE is high, i.e., a scan shift operation mode. The latched scan input data SI, which is passed through the latch circuit 11, is outputted from the latch circuit 11 as a scan output data SO.
On the other hand, the latch circuit 10 latches the input data D, and outputs the latched input data D as an output data Q when the scan enable signal SE is Low, i.e., a normal operation mode. During the normal operation mode, the scan shift operation is not performed. Also, the latch circuit 11 does not operate since the supply of the pulse clock signal PCLK is stopped.
Since the operation of the latch circuit 11 is stopped at the time of the normal operation mode, the power consumption may be suppressed.
When the pulse latch circuit 1 is applied to detection of deterioration of the circuit to be tested of the LSI, for example, two pulse latch circuits 1 are inserted in parallel in an output bus of the circuit to be tested. Also, the pulse clock signals PCLK, the phase difference of each of PCLK is different from each other, are inputted into each of the two pulse latch circuits 1, and then the deterioration of the circuit to be tested is detected.